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ISL8843
Data Sheet October 19, 2005 FN9238.0
Industry Standard Single-Ended Current Mode PWM Controller
The ISL8843 is an industry standard drop-in replacement for the popular 28C43 and 18C43 PWM controllers suitable for a wide range of power conversion applications including boost, flyback, and isolated output configurations. Its fast signal propagation and output switching characteristics make this an ideal product for existing and new designs. Features include 30V operation, low operating current, 90A start-up current, adjustable operating frequency to 2MHz, and high peak current drive capability with 20ns rise and fall times.
PART NUMBER ISL8843 RISING UVLO 8.4V MAX. DUTY CYCLE 100%
Features
* 1A MOSFET gate driver * 90A start-up current, 125A maximum * 35ns propagation delay current sense to output * Fast transient response with peak current mode control * 30V operation * Adjustable switching frequency to 2MHz * 20ns rise and fall times with 1nF output load * Trimmed timing capacitor discharge current for accurate deadtime/maximum duty cycle control * 1.5MHz bandwidth error amplifier * Tight tolerance voltage reference over line, load, and temperature * 3% current limit threshold * Pb-free plus anneal available and ELV, WEEE, RoHS Compliant
Ordering Information
PART NUMBER ISL8843ABZ (See Note) ISL8843AUZ (See Note) PART MARKING 8843 ABZ 8843Z TEMP. PKG. RANGE (C) PACKAGE DWG. # -40 to 105 -40 to 105 -55 to 125 -55 to 125 8 Ld SOIC (Pb-free) M8.15
Applications
* Telecom and datacom power * Wireless base station power * File server power * Industrial power systems * PC power supplies * Isolated buck and flyback regulators * Boost regulators
8 Ld MSOP M8.118 (Pb-free) 8 Ld SOIC (Pb-free) M8.15
ISL8843MBZ 8843 MBZ (See Note) ISL8843MUZ 843MZ (See Note)
8 Ld MSOP M8.118 (Pb-free)
Add -T to part number for Tape and Reel packaging. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
ISL8843 (8 LD SOIC, MSOP) TOP VIEW
COMP 1 FB 2 CS 3 RTCT 4 8 VREF 7 VDD 6 OUT 5 GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005 All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram
VDD START/STOP UV COMPARATOR + BG + GND 2.5V A A=0.5 VDD OK ENABLE
VREF 5.00 V
VREF
VREF FAULT
+
VREF UV COMPARATOR 4.65V 4.80V
CS
100mV 5%
+ -
PWM COMPARATOR
+ BG
2
FN9238.0 October 19, 2005
FB
+ ERROR AMPLIFIER VF Total = 1.15V
2R
+ R
ISL8843
1.1V 3% CLAMP
COMP OUT
S R Q
36K
Q
VREF 100K 2.9V 1.0V ON 150K OSCILLATOR COMPARATOR < 10nS RTCT 8.4mA ON + CLOCK
100 nS FALLING EDGE DELAY
RESET DOMINANT
P/N 8843
UVLO ON/OFF 8.4 / 7.6V
Typical Application - 48V Input Dual Output Flyback
CR5 +3.3V T1 VIN+ R3 C4 CR4 C17 + C22 + C20 RETURN CR6 R1 36-75V C6 C1 C3 Q1 U2 R16 R17 R19 C14 R18 C21 R21 +1.8V + C15 + C16
C2 C5
CR2
C19
3
VINR6 Q3 VR1
FN9238.0 October 19, 2005
R4
R22 U3 R27
C13
R15
ISL8843
R20 U4 R26 COMP VREF CS FB V DD OUT
RTCT GND ISL8843
CR1
R10
C12 C8 R13 C11
ISL8843
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +30.0V OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD + 0.3V Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A ESD Classification Human Body Model (Per JESD22-A114C.01) . . . . . . . . . . .2000V Machine Model (Per EIA/JESD22-A115-A) . . . . . . . . . . . . . .200V Charged Device Model (Per JESD22-C191-A) . . . . . . . . . .1000V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Maximum Junction Temperature . . . . . . . . . . . . . . . . -55C to 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C (SOIC, MSOP - Lead Tips Only)
Operating Conditions
Temperature Range ISL8843AxZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to 105C ISL8843MxZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55C to 125C Supply Voltage Range (Typical) ISL8843 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V - 30V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are with respect to GND.
Electrical Specifications
ISL8843A - Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. VDD = 15V, RT = 10k, CT = 3.3nF, TA = -40 to 105C (Note 3) Typical values are at TA = 25C
TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER UNDERVOLTAGE LOCKOUT START Threshold STOP Threshold Hysteresis Startup Current, IDD Operating Current, IDD Operating Supply Current, ID REFERENCE VOLTAGE Overall Accuracy Long Term Stability Current Limit, Sourcing Current Limit, Sinking CURRENT SENSE Input Bias Current CS Offset Voltage COMP to PWM Comparator Offset Voltage Input Signal, Maximum Gain, ACS = VCOMP/VCS CS to OUT Delay ERROR AMPLIFIER Open Loop Voltage Gain Unity Gain Bandwidth Reference Voltage
8.0 7.3 VDD < START Threshold (Note 4) Includes 1nF GATE loading -
8.4 7.6 0.8 90 2.9 4.75
9.0 8.0 125 4.0 5.5
V V V A mA mA
Over line (VDD = 12V to 18V), load, temperature TA = 125C, 1000 hours (Note 5)
4.925 -20 5
5.000 5 -
5.050 -
V mV mA mA
VCS = 1V VCS = 0V (Note 5) VCS = 0V (Note 5) 0 < VCS < 910mV, VFB = 0V
-1.0 95 0.80 0.97 2.5 -
100 1.15 1.00 3.0 35
1.0 105 1.30 1.03 3.5 55
A mV V V V/V ns
(Note 5) (Note 5) VFB = VCOMP
60 1.0 2.475
90 1.5 2.500
2.530
dB MHz V
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FN9238.0 October 19, 2005
ISL8843
Electrical Specifications ISL8843A - Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. VDD = 15V, RT = 10k, CT = 3.3nF, TA = -40 to 105C (Note 3) Typical values are at TA = 25C (Continued)
TEST CONDITIONS VFB = 0V VCOMP = 1.5V, VFB = 2.7V VCOMP = 1.5V, VFB = 2.3V VFB = 2.3V VFB = 2.7V Frequency = 120Hz, VDD = 12V to 18V (Note 5) MIN -1.0 1.0 -0.4 4.80 0.4 60 TYP -0.2 80 MAX 1.0 VREF 1.0 UNITS A mA mA V V dB
PARAMETER FB Input Bias Current COMP Sink Current COMP Source Current COMP VOH COMP VOL PSRR OSCILLATOR Frequency Accuracy Frequency Variation with VDD Temperature Stability Amplitude, Peak to Peak RTCT Discharge Voltage (Valley Voltage) Discharge Current OUTPUT Gate VOH Gate VOL Peak Output Current Rise Time Fall Time GATE VOL UVLO Clamp Voltage PWM Maximum Duty Cycle Minimum Duty Cycle NOTES:
Initial, TA = 25C TA= 25C, (F30V - F9V)/F30V (Note 5) Static Test Static Test RTCT = 2.0V
48 6.5
51 0.2 1.75 1.0 7.8
53 1.0 5 8.5
kHz % % V V mA
VDD - OUT, IOUT = -200mA OUT - GND, IOUT = 200mA COUT = 1nF (Note 5) COUT = 1nF (Note 5) COUT = 1nF (Note 5) VDD = 5V, ILOAD = 1mA COMP = VREF COMP = GND
-
1.0 1.0 1.0 20 20 -
2.0 2.0 40 40 1.2
V V A ns ns V
93.5 -
95 -
0
% %
3. Specifications at -40C and 105C are guaranteed by 25C test with margin limits. 4. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current. 5. Guaranteed by design, not 100% tested in production.
Electrical Specifications
ISL8843M - Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. VDD = 15V, RT = 10k, CT = 3.3nF, TA = -55 to 125C (Note 6), Typical values are at TA = 25C
TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER UNDERVOLTAGE LOCKOUT START Threshold STOP Threshold Hysteresis Startup Current, IDD Operating Current, IDD Operating Supply Current, ID REFERENCE VOLTAGE Overall Accuracy
8.0 7.3 VDD < START Threshold (Note 7) Includes 1nF GATE loading -
8.4 7.6 0.8 90 2.9 4.75
9.0 8.0 125 4.0 5.5
V V V A mA mA
Over line (VDD = 12V to 18V), load, temperature
4.900
5.000
5.050
V
5
FN9238.0 October 19, 2005
ISL8843
Electrical Specifications ISL8843M - Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. VDD = 15V, RT = 10k, CT = 3.3nF, TA = -55 to 125C (Note 6), Typical values are at TA = 25C (Continued)
TEST CONDITIONS TA = 125C, 1000 hours (Note 8) MIN -20 5 TYP 5 MAX UNITS mV mA mA
PARAMETER Long Term Stability Current Limit, Sourcing Current Limit, Sinking CURRENT SENSE Input Bias Current CS Offset Voltage COMP to PWM Comparator Offset Voltage Input Signal, Maximum Gain, ACS = VCOMP/VCS CS to OUT Delay ERROR AMPLIFIER Open Loop Voltage Gain Unity Gain Bandwidth Reference Voltage FB Input Bias Current COMP Sink Current COMP Source Current COMP VOH COMP VOL PSRR OSCILLATOR Frequency Accuracy Frequency Variation with VDD Temperature Stability Amplitude, Peak to Peak RTCT Discharge Voltage (Valley Voltage) Discharge Current OUTPUT Gate VOH Gate VOL Peak Output Current Rise Time Fall Time GATE VOL UVLO Clamp Voltage PWM Maximum Duty Cycle Minimum Duty Cycle NOTES:
VCS = 1V VCS = 0V (Note 8) VCS = 0V (Note 8) 0 < VCS < 910mV, VFB = 0V
-1.0 95 0.80 0.97 2.5 -
100 1.15 1.00 3.0 35
1.0 105 1.30 1.03 3.5 60
A mV V V V/V ns
(Note 8) (Note 8) VFB = VCOMP VFB = 0V VCOMP = 1.5V, VFB = 2.7V VCOMP = 1.5V, VFB = 2.3V VFB = 2.3V VFB = 2.7V Frequency = 120Hz, VDD = 12V to 18V (Note 8)
60 1.0 2.460 -1.0 1.0 -0.4 4.80 0.4 60
90 1.5 2.500 -0.2 80
2.535 1.0 VREF 1.0 -
dB MHz V A mA mA V V dB
Initial, TA = 25C TA = 25C, (F30V - F9V)/F30V (Note 8) Static Test Static Test RTCT = 2.0V
48 6.2
51 0.2 1.75 1.0 8.0
53 1.0 5 8.5
kHz % % V V mA
VDD - OUT, IOUT = -200mA OUT - GND, IOUT = 200mA COUT = 1nF (Note 8) COUT = 1nF (Note 8) COUT = 1nF (Note 8) VDD = 5V, ILOAD = 1mA COMP = VREF COMP = GND
-
1.0 1.0 1.0 20 20 -
2.0 2.0 40 40 1.2
V V A ns ns V
93.5 -
95 -
0
% %
6. Specifications at -55C and 125C are guaranteed by 25C test with margin limits. 7. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current. 8. Guaranteed by design, not 100% tested in production.
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FN9238.0 October 19, 2005
ISL8843 Typical Performance Curves
1.01 NORMALIZED VREF 1.001 1.000 0.999 0.998 0.997 0.996 0.98 -60 -40 -20 0.995 -60 -40 -20 0 20 40 60 80 100 120 140
NORMALIZED FREQUENCY
1
0.99
0
20
40
60
80
100 120 140
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 1. FREQUENCY vs TEMPERATURE
FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE
1*103
NORMALIZED EA REFERENCE
FREQUENCY (kHz)
1.001
CT = 100pF 100 220pF 330pF 470pF 1.0nF 10 2.2nF 3.3nF 4.7nF 6.8nF
1.000
0.998
0.997
0.996 -60 -40 -20
0
20
40
60
80 100 120 140
1
1
TEMPERATURE (C)
10 RT (k)
100
FIGURE 3. EA REFERENCE vs TEMPERATURE
FIGURE 4. RTCT vs FREQUENCY
Pin Descriptions
RTCT - This is the oscillator timing control pin. The operational frequency and maximum duty cycle are set by connecting a resistor, RT, between VREF and this pin and a timing capacitor, CT, from this pin to GND. The oscillator produces a sawtooth waveform with a programmable frequency range up to 2.0MHz. The charge time, TC, the discharge time, TD, the switching frequency, f, and the maximum duty cycle, Dmax, can be approximated from the following equations:
T C 0.533 * RT * CT 0.008 * RT - 3.83 - RT * CT * ln ---------------------------------------------- 0.008 * RT - 1.71 (EQ. 1)
The formulae have increased error at higher frequencies due to propagation delays. Figure 4 may be used as a guideline in selecting the capacitor and resistor values required for a given frequency. COMP - COMP is the output of the error amplifier and the input of the PWM comparator. The control loop frequency compensation network is connected between the COMP and FB pins. FB - The output voltage feedback is connected to the inverting input of the error amplifier through this pin. The non-inverting input of the error amplifier is internally tied to a reference voltage. CS - This is the current sense input to the PWM comparator. The range of the input signal is nominally 0 to 1.0V and has an internal offset of 100mV. GND - GND is the power and small signal reference ground for all functions.
T
D
(EQ. 2)
f = 1 (TC + TD)
D = TC * f
(EQ. 3) (EQ. 4)
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FN9238.0 October 19, 2005
ISL8843
OUT - This is the drive output to the power switching device. It is a high current output capable of driving the gate of a power MOSFET with peak currents of 1.0A. This GATE output is actively held low when VDD is below the UVLO threshold. VDD - VDD is the power connection for the device. The total supply current will depend on the load applied to OUT. Total IDD current is the sum of the operating current and the average output current. Knowing the operating frequency, f, and the MOSFET gate charge, Qg, the average output current can be calculated from:
I OUT = Qg x f (EQ. 5)
Gate Drive
The ISL8843 is capable of sourcing and sinking 1A peak current. To limit the peak current through the IC, an optional external resistor may be placed between the totem-pole output of the IC (OUT pin) and the gate of the MOSFET. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET's input capacitance.
Slope Compensation
For applications where the maximum duty cycle is less than 50%, slope compensation may be used to improve noise immunity, particularly at lighter loads. The amount of slope compensation required for noise immunity is determined empirically, but is generally about 10% of the full scale current feedback signal. For applications where the duty cycle is greater than 50%, slope compensation is required to prevent instability. Slope compensation may be accomplished by summing an external ramp with the current feedback signal or by subtracting the external ramp from the voltage feedback error signal. Adding the external ramp to the current feedback signal is the more popular method. From the small signal current-mode model [1] it can be shown that the naturally-sampled modulator gain, Fm, without slope compensation, is
1 Fm = ------------------SnTsw (EQ. 6)
To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. VREF - The 5.00V reference voltage output. +1.0/-1.5% tolerance over line, load and operating temperature. Bypass to GND with a 0.1F to 3.3F capacitor to filter this output as needed.
Functional Description
Features
The ISL8843 current mode PWM makes an ideal choice for low-cost flyback and forward topology applications. With its greatly improved performance over industry standard parts, it is the obvious choice for new designs or existing designs which require updating.
Oscillator
The ISL8843 has a sawtooth oscillator with a programmable frequency range to 2MHz, which can be programmed with a resistor from VREF and a capacitor to GND on the RTCT pin. (Please refer to Figure 4 for the resistor and capacitance required for a given frequency.)
where Sn is the slope of the sawtooth signal and Tsw is the duration of the half-cycle. When an external ramp is added, the modulator gain becomes
1 1 Fm = -------------------------------------- = --------------------------( Sn + Se )Tsw m c SnTsw (EQ. 7)
Soft-Start Operation
Soft-start must be implemented externally. One method, illustrated below, clamps the voltage on COMP.
where Se is slope of the external ramp and
Se m c = 1 + ------Sn (EQ. 8)
VREF ISL8843
COMP
The criteria for determining the correct amount of external ramp can be determined by appropriately setting the damping factor of the double-pole located at the switching frequency. The double-pole will be critically damped if the Q-factor is set to 1, over-damped for Q < 1, and underdamped for Q > 1. An under-damped condition may result in current loop instability.
1 Q = ------------------------------------------------ ( m c ( 1 - D ) - 0.5 ) (EQ. 9)
GND
where D is the percent of on time during a switching cycle. Setting Q = 1 and solving for Se yields
FIGURE 5. SOFT-START 1 1 S e = S n -- + 0.5 ------------ - 1 1-D (EQ. 10)
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FN9238.0 October 19, 2005
ISL8843
Since Sn and Se are the on time slopes of the current ramp and the external ramp, respectively, they can be multiplied by Ton to obtain the voltage change that occurs during Ton.
1 1 V e = V n -- + 0.5 ------------ - 1 1 -D
VREF
(EQ. 11)
ISL8843
R9
where Vn is the change in the current feedback signal (I) during the on time and Ve is the voltage that must be added by the external ramp. For a flyback converter, Vn can be solved for in terms of input voltage, current transducer components, and primary inductance, yielding
D T SW V IN R CS 1 1 -V e = --------------------------------------------------- -- + 0.5 ------------ - 1 1 -D Lp V (EQ. 12)
CS R6 RTCT C4
FIGURE 6. SLOPE COMPENSATION
where RCS is the current sense resistor, TSW is the switching frequency, Lp is the primary inductance, VIN is the minimum input voltage, and D is the maximum duty cycle. The current sense signal at the end of the ON time for CCM operation is:
( 1 D ) VO T N S R CS sw V CS = ------------------------ I O + -------------------------------------------- NP 2L s V (EQ. 13)
Assuming the designer has selected values for the RC filter (R6 and C4) placed on the CS pin, the value of R9 required to add the appropriate external ramp can be found by superposition.
1.9D R6 V e = -----------------------R6 + R9 V (EQ. 16)
Rearranging to solve for R9 yields
( 1.9D - V e ) R6 R9 = ------------------------------------------Ve (EQ. 17)
where VCS is the voltage across the current sense resistor, Ls is the secondary winding inductance, and IO is the output current at current limit. Equation 13 assumes the voltage drop across the output rectifier is negligible. Since the peak current limit threshold is 1.00V, the total current feedback signal plus the external ramp voltage must sum to this value when the output load is at the current limit threshold.
V e + V CS = 1 (EQ. 14)
The value of RCS determined in Equation 15 must be rescaled so that the current sense signal presented at the CS pin is that predicted by Equation 13. The divider created by R6 and R9 makes this necessary.
R6 + R9 R CS = --------------------- R CS R9 (EQ. 18)
Example: VIN = 12V VO = 48V Ls = 800H Ns/Np = 10 Lp = 8.0H IO = 200mA Switching Frequency, Fsw = 200kHz Duty Cycle, D = 28.6% R6 = 499 Solve for the current sense resistor, RCS, using Equation 15 RCS = 295m.
Substituting Equations and 13 into Equation 14 and solving for RCS yields
1 R CS = -------------------------------------------------------------------------------------------------------------------------------------------------------1 -- + 0.5 N D T sw V IN ( 1 - D ) V O T sw s --------------------------------- ----------------- - 1 + ------ I O + --------------------------------------------- 1-D N Lp 2L s p (EQ. 15)
Adding slope compensation is accomplished in the ISL8843 using an external buffer transistor and the RTCT signal. A typical application sums the buffered RTCT signal with the current sense feedback and applies the result to the CS pin as shown in Figure 6.
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FN9238.0 October 19, 2005
ISL8843
Determine the amount of voltage, Ve, that must be added to the current feedback signal using Equation 12. Ve = 92.4mV Using Equation 17, solve for the summing resistor, R9, from CT to CS. R9 = 2.43k Determine the new value of RCS, R'CS, using Equation 18. R'CS = 356m Additional slope compensation may be considered for design margin. The above discussion determines the minimum external ramp that is required. The buffer transistor used to create the external ramp from RTCT should have a sufficiently high gain (>200) so as to minimize the required base current. Whatever base current is required reduces the charging current into RTCT and will reduce the oscillator frequency.
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V. When a Fault is detected OUT is disabled. When VREF exceeds 4.80V, the Fault condition clears, and OUT is enabled.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents associated with the output stage. VDD should be bypassed directly to GND with good high frequency capacitors.
References
[1] Ridley, R., "A New Continuous-Time Model for Current Mode Control", IEEE Transactions on Power Electronics, Vol. 6, No. 2, April 1991.
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FN9238.0 October 19, 2005
ISL8843 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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FN9238.0 October 19, 2005
ISL8843 Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -BE
INCHES SYMBOL A
ABC
MILLIMETERS MIN 0.94 0.05 0.75 0.25 0.09 2.95 2.95 MAX 1.10 0.15 0.95 0.36 0.20 3.05 3.05 NOTES 9 3 4 6 7 15o 6o Rev. 2 01/03
MIN 0.037 0.002 0.030 0.010 0.004 0.116 0.116
MAX 0.043 0.006 0.037 0.014 0.008 0.120 0.120
INDEX AREA
12 TOP VIEW
0.20 (0.008)
A1 A2
4X
0.25 (0.010) GAUGE PLANE SEATING PLANE -CA A2
R1 R
b c D E1
4X
L L1
e E L L1 N R
0.026 BSC 0.187 0.016 8 0.003 0.003 5o 0o 15o 6o 0.199 0.028
0.65 BSC 4.75 0.40 8 0.07 0.07 5o 0o 5.05 0.70
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
R1 0
SIDE VIEW
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN9238.0 October 19, 2005

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